AMD/IOMMU: use bit field for control register
authorJan Beulich <jbeulich@suse.com>
Wed, 31 Jul 2019 11:15:04 +0000 (13:15 +0200)
committerJan Beulich <jbeulich@suse.com>
Wed, 31 Jul 2019 11:15:04 +0000 (13:15 +0200)
commit08344ec71cad07829855fb7927faaafd26189798
tree84dfe7cbf32e7432ddeebf65cc0f87e246255db2
parentc69363b2ac7e5ed88908a304e6903f5842c9805e
AMD/IOMMU: use bit field for control register

Also introduce a field in struct amd_iommu caching the most recently
written control register. All writes should now happen exclusively from
that cached value, such that it is guaranteed to be up to date.

Take the opportunity and add further fields. Also convert a few boolean
function parameters to bool, such that use of !! can be avoided.

Because of there now being definitions beyond bit 31, writel() also gets
replaced by writeq() when updating hardware.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
Acked-by: Brian Woods <brian.woods@amd.com>
xen/drivers/passthrough/amd/iommu_guest.c
xen/drivers/passthrough/amd/iommu_init.c
xen/include/asm-x86/amd-iommu.h
xen/include/asm-x86/hvm/svm/amd-iommu-defs.h